// +FHDR------------------------------------------------------------
//                 Copyright (c) 2024 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : test.v
// Author        : ICer
// Created On    : 2024-03-11 17:39
// Last Modified : 2024-03-11 17:54 by ICer
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------


module test #(
    //parameter
)( /*AUTOARG*/
   // Outputs
   data, data1, data2,
   // Inputs
   clk, rst_n, sel, mux1, mux2
   );

// ----------------------------------------------------------------
// Interface declare
// ----------------------------------------------------------------
input clk;
input rst_n;

output reg[WD*NUM -1:0] data;
output [NUM+:4]data1,data2;
input sel;
output wire[8-:WD]mux1, mux2;

// ----------------------------------------------------------------
// Wire declare
// ----------------------------------------------------------------
parameter WD = 7;
parameter NUM = 5;

// ----------------------------------------------------------------
// AUTO declare
// ----------------------------------------------------------------
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/

endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// End:

